1. Field of the Invention
The present invention relates to the fabrication of a vertically stacked microelectronic device layer structure on a gallium arsenide (GaAs) substrate which enables the fabrication of three dimensional microelectronic devices therein.
2. Description of the Related Art
The development of microelectronic device fabrication technology on GaAs substrates, especially in the area of monolithic microwave integrated circuits (MMIC), is progressing to the point at which the two dimensional packing density of components such as single chip mixers, local oscillators and amplifiers is approaching a saturation value. Increasing the component density on a chip requires that the device structure be expanded from two to three dimensions.
Three dimensional epitaxial device structures have been proposed on silicon substrates, such as described in U.S. Pat. No. 4,771,013, entitled "PROCESS OF MAKING A DOUBLE HETEROJUNCTION 3-D I.sup.2 L BIPOLAR TRANSISTOR WITH A SI/GE SUPERLATTICE", issued Sep. 13, 1988, to P. Curran. However, the epitaxial deposition technologies used for silicon typically require processing at temperatures in excess of 1,000.degree. C., which is far above the dissociation temperature (550.degree. C.) of GaAs, and the typical annealing temperatures for GaAs in the range of 800.degree.-900.degree. C.
Vertically stacked epitaxial structures may be formed on GaAs substrates using vapor phase epitaxy or organometallic chemical vapor deposition (OMCVD) at lower temperatures. However, epitaxy is an expensive and one at-a-time process. Epitaxial layers grown by these processes are highly non-uniform in thickness, and doping is not very reproducible. In addition, epitaxial structures are non-planar, and have to be combined with other components in a hybrid manner due to the inherent incompatibility of the profiles.
High density integrated circuits are conventionally fabricated on GaAs substrate wafers which must be thinned down to approximately 100 micrometers to provide sufficient power dissipation. Electrically conductive vertical interconnects (vias) must be formed through the wafers to dissipate power from the devices on the frontside to a ground plane or heat sink on the backside. The thinning process results in a high damage rate during manufacture of the integrated circuits. The vias make the wafers even more fragile.